//v2ch dpram 0~287 128
module decode_dpram_v2ch(
i_r_clk,
i_w_clk,
i_r_en,
i_w_en,
i_r_addr,
i_w_addr,
i_w_data,
o_r_data  
);

input i_r_clk;
input i_w_clk;
input i_r_en;
input i_w_en;
input [8:0] i_r_addr;
input [8:0] i_w_addr;
input [0:127] i_w_data;
            
output reg [0:127] o_r_data;

reg [0:127] mem[287:0]; 

always@(posedge i_w_clk) begin
if(i_w_en == 1'b1)
    mem[i_w_addr] <=  i_w_data;
end

always@(posedge i_r_clk) begin
if(i_r_en == 1'b1)
    o_r_data <=  mem[i_r_addr];
end
endmodule